With the development of panel display, a display with high resolution and narrow frame has been a trend, and integration of a gate driving circuit on a panel is a most important solution in order to realize the display with the high resolution and narrow frame. With respect to an a-si (amorphous silicon) technique and a p-si (poly-silicon) technique, various existing mature shift register circuits may achieve this object very well. An oxide TFT (transistor), as a very potential semiconductor technique, has a lower cost as compared with the p-si technique and a higher mobility as compared with the a-si technique, and therefore has been paid more and more attention, it may likely become a mainstream technique of a backboard driving for a flexible display such as an OLED (Organic Light-Emitting Diode) in future. However, the oxide TFT is a depletion transistor, while the aforementioned a-si TFT and p-si TFT are enhancement transistors.
FIG. 1 is a circuit diagram of a traditional basic shift register unit. As illustrated in FIG. 1, the basic shift register unit comprises a pulling-up thin film transistor, a pulling-down thin film transistor, a first capacitor C1, a pulling-up control thin film transistor T100, a pulling-down control thin film transistor T200, a second capacitor C2, a first clock signal input terminal CK, a second clock signal input terminal CKB, an input terminal Input, a reset terminal Reset and an output terminal Output;
a pulling-up (PU) node is a node connected with a gate of the pulling-up thin film transistor, and a pulling-down (PD) node is a node connected with a gate of the pulling-down thin film transistor; and
a start signal STV is input from the input terminal Input, VGL is a low level.
FIG. 2 is a timing diagram of respective signals when the basic shift register unit shown in FIG. 1 operates, in which VGH is a high level.
When a circuit of the basic shift register unit is made by an enhancement TFT technique, the circuit of the basic shift register unit may operate normally, as illustrated in solid-line parts in FIG. 2; while if the circuit is made by the oxide transistors (the depletion transistors), the circuit is disabled because a pulling-down transistor can not be turned off. It can be found from the timing graphs for the PU node and the output Output that the case of being not turned off exists.
Differences between the enhancement transistor and the depletion transistor are as illustrated in FIGS. 3 and 4. Herein, FIG. 3 is a characteristic graph of the enhancement transistor, a vertical axis in FIG. 3 denotes drain current iD of the enhancement transistor while a horizontal axis in FIG. 3 denotes gate-source voltage Vgs of the enhancement transistor, and it can be seen from the FIG. 3 that iD is zero when Vgs is zero, which indicates that the enhancement transistor is turned off completely as the Vgs is zero. FIG. 4 is a characteristic graph of the depletion transistor, similarly a vertical axis in FIG. 4 denotes drain current iD of the depletion transistor while a horizontal axis in FIG. 4 denotes gate-source voltage Vgs of the depletion transistor, but FIG. 4 shows that iD is much greater than zero when Vgs is zero, and iD would be zero only when the gate-source voltage Vgs is −6V. Therefore, the depletion transistor is still in a turned-on state and can not be turned off when the gate-source voltage Vgs is 0, such that the existing circuit which may operate normally with the a-si technique or the p-si technique has a large leakage current because the oxide transistor can not be turned off when it is made by the oxide transistor. As a result, the circuit of the traditional basic shift register unit as illustrated in FIG. 1 is not applicable any more.